july 2003 R8051 8-bit risc-like microcontroller core the R8051 is a fast, small, single-chip, 8-bit microcontroller that executes all asm51 instructions. it has the same instruction set as the 80c31, but its risc-like design executes operations an average of 8 times faster. the R8051 provides software and hardware interrupts, a serial communications in- terface, two timers, and intel peripherals support. on-chip debugging is an option. the microcode-free design was developed for easy reuse and is available optimized for several lattice devices, with competitive utilization and performance characteris- tics. scan insertion is also straightforward. applications ? embedded microcontroller systems ? data computation and transfer ? communication systems ? professional audio and video block diagram control unit 8-bit instruction decoder reduced instruction cycle time up to 12 times 8-bit arithmetic-logic unit 32-bit input/output ports four 8-bit i/o ports alternate port functions such as external interrupts and se- rial interface are separated, providing extra port pins when compared with the standard 8051 two 16-bit timer/counters serial peripheral interfaces in full duplex mode synchronous mode, fixed baud rate 8-bit uart mode, variable baud rate 9-bit uart mode, fixed & variable baud rate multiprocessor communica- tion two priority/five sources inter- rupt controller internal data memory interface can address up to 256 bytes of read/write data memory space external memory interface can address up to 64 kb of external program memory can address up to 64 kb of external data memory de-multiplexed address/data bus to allow easy connection to memories variable length movx to ac- cess fast/slow ram/ or peripherals wait cycles to access fast/slow rom dual data pointer register program memory write mode special function registers in- terface - services up to 104 external sfrs power management unit C idle and stop modes jtag debugging interface (op- tional) cycle fetch instr ports p0 p 0i p1 p2 p3 p 1i p 2i p 3i p 0o p 1o p 2o p 3o serial scon sbuf i sr i p ie t f1, ie1 t f0, ie0 control_unit alu cycle instr ram _ sfr _ control ramdatai ramdatao ramaddr ramoe ramwe sfrdatai sfrdatao sfradd r sfroe sfrwe s p clock _ control pcon reset clk timer tl0 tl1 th0 th1 tcon tmod memory_control acc b psw d p tr p c instrre g r iti rxdo txd rxdi c y cle fetch instr memdatao memaddr mempsw r memw r memr d mempsr d memdatai t1 t0 int0 int1 pmu clkcpu clkcpuo clkper clkpero d p tr1 mempsac k d p s oci debugreq debugstep debugprog debugac k fetc h flus h acc (optional)
cast, inc. 11 stonewall court woodcliff lake, nj 076747 usa tel 201-391-8300 fax 201-391-8694 copyright ? cast, inc. 2003, all rights reserved. contents subject to change without notice. july 2003 http://www.latticesemi.com implementation results performance the architecture eliminates redundant bus states and imple- ments parallel execution of fetch and execution phases. since a cycle is aligned with memory fetch when possible, most of the 1-byte instructions are performed in a single cycle. the R8051 uses 1 clock per cycle. this leads to performance improvement of rate 8x (in terms of mips) with respect to the intel device working with the same clock frequency (the original 8051 had a 12-clock architecture. a machine cycle needed 12 clocks and most instructions were either one or two machine cycles. thus except for the mul and div instructions, the 8051 used either 12 or 24 clocks for each instruction. furthermore, each cycle in the 8051 used two memory fetches. in many cases the second fetch was dummy, and extra clocks were wasted). the table below illustrates the speed advantage of the R8051 over the standard 8051. a speed advantage of 12 means that the R8051 performs the same instruction twelve times faster that the 8051. speed advantage number of instructions number of opcodes 24 1 1 12 27 83 9.6 2 2 81638 64489 4.8 1 2 41831 329 average: 8.0 sum: 111 sum: 255 implementation results the following are typical performance and utilization results using lattice ispxpga? and orca? devices. lattice device lut- 4s regis- ters pfus sysmem ebrs external i/os speed (f max , mhz) lfx500c-4 4398 655 1160 5 71 26.7 or4e02-3 4389 476 606 5 71 33.3 support the core as delivered is warranted against defects for one year from purchase. thirty days of phone and email technical sup- port are included, starting with the first interaction. additional maintenance and support options are available. verification the R8051 cores functionality was verified by means of a pro- prietary hardware modeler. the same stimulus was applied to a hardware model that contained the original intel 80c31 chip, and the results compared with the cores simulation outputs. the core has also been successfully implemented in commer- cial and prototype systems. deliverables the core includes everything required for successful imple- mentation: ? post-synthesis edif netlist (firm core) optimized for a spe- cific lattice device (hdl rtl source code (soft core) is also available) ? testbenches (self-checking) ? simulation script, vectors, and expected results ? synthesis (soft) or place and route (firm) script ? comprehensive user documentation related information ? cmos single-chip 8-bit microcontrollers, philips, 1996. ? addendum to the mcs?51 microcontroller family, intel, 1996. ? 8-bit embedded controllers, intel, 1990
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